1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming buried contacts having high tolerance to buried contact mask misalignment in the fabrication of integrated circuits.
2. Description of the Prior Art
Referring to FIG. 1, a typical buried contact is formed by depositing a doped layer of polysilicon 16 over and on the planned buried contact region in a semiconductor substrate 10 and heating the structure. The buried contact region 20 is doped by outdiffusion of dopants from the doped polysilicon layer 16 into the silicon substrate. The doped polysilicon layer is allowed to remain on the buried contact region as its contact. Gate electrode 18 and source/drain region 22 are also formed. If there is misalignment of the mask during etching of the polysilicon 16, a portion of the semiconductor substrate within the buried contact area will be exposed. During polysilicon overetching, a buried contact trench 25 will be etched. If the trench is deep enough, it may cause disconnection between the buried contact 20 and the source/drain region 22.
U.S. Pat. No. 5,350,712 to Shibata teaches the use of an additional metal width around a metal line to overcome mask misalignment problems causing etching of the semiconductor substrate.